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11/30/04 international rectifier ? ?? ? 233 kansas street , el se g undo , ca 90245 usa (photo shown without heatsink) IRDCIP1203-A: 400khz, 15a, synchronous buck converter using ip1203 overview this reference design is capable of delivering a continuous current of 15a (with heatsink) or 12a (without heatsink) at an ambient temperature of 45oc and airflow of 300lfm. figures 1C20 provide performance graphs, thermal images, and waveforms. figures 21C33 and table 1 are provided to engineers as design references for implementing an ip1203 solution. the components installed on this demoboard were selected based on operating at an input voltage of 12v (+/-10%) and a switching frequency of 400khz (+/-15%). major changes from these set points may require optimizing the control loop and/or adjusting the values of input/output filters in order to meet the users specific application requirements. refer to the ip1203 datasheet user design guidelines section for more information. note: the 16-pin connector (con1) is used only for production test purposes and should not be used for evaluation of this demoboard. demoboard quick start guide initial settings: vout is set to 1.8v, but can be adjusted from 1.0v to 3.3v by changing the values of r3 and r7 according to the following formula: r3 = r7 = (15k * 0.8) / (vout - 0.8) the switching frequency is set to 400khz, but can be adjusted by changing the value of r10. the graph in figure 22 shows the relationship between r10 and the switching frequency. power up procedure: 1. apply input voltage across vin and pgnd. 2. apply load across vout pads and pgnd pads. 3. adjust load to desired level. see recommendations below. IRDCIP1203-A recommended operating conditions (refer to the ip1203 datasheet for maximum operating conditions) input voltage: 5.5v C 13.2v output voltage: 1.0 C 3.3v switching freq: 400khz output current: this reference design is capable of delivering a continuous current of 15a (with heatsink) or 12a (without heatsink) at an ambient temperature of 45oc and airflow of 300lfm. downloaded from: http:///
www.irf.com 2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0123456789101112131415 total output current (a) power loss (w) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=5.5v fsw=400khz ta=25oc 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0123456789101112131415 total output current (a) power loss (w) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=8.0v fsw=400khz ta=25oc 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0123456789101112131415 total output current (a) power loss (w) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=12v fsw=400khz ta=25oc fig. 1: power loss vs. output current for vin=5.5v fig. 2: power loss vs. output current for vin=8.0v fig. 3: power loss vs. output current for vin=12.0v downloaded from: http:///
3 www.irf.com 75% 76% 77% 78% 79% 80% 81% 82% 83% 84% 85% 86% 87% 88% 89% 90% 91% 92% 93% 94% 95% 96% 0123456789101112131415 total output current (a) efficiency (%) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=5.5v fsw=400khz ta=25oc 75% 76% 77% 78% 79% 80% 81% 82% 83% 84% 85% 86% 87% 88% 89% 90% 91% 92% 93% 94% 95% 96% 0123456789101112131415 total output current (a) efficiency (%) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=8.0v fsw=400khz ta=25oc 75% 76% 77% 78% 79% 80% 81% 82% 83% 84% 85% 86% 87% 88% 89% 90% 91% 92% 93% 94% 95% 96% 0123456789101112131415 total output current (a) efficiency (%) vo=1.0v vo=1.3v vo=1.8v vo=2.5v vo=3.3v conditions: vin=12v fsw=400khz ta=25oc fig. 4: efficiency vs. output current for vin=5.5v fig. 5: efficiency vs. output current for vin=8.0v fig. 6: efficiency vs. output current for vin=12.0v downloaded from: http:///
www.irf.com 4 99.0% 99.1% 99.2% 99.3% 99.4% 99.5% 99.6% 99.7% 99.8% 99.9% 100.0% 01234567891 01 11 21 31 41 5 output current (a) conditions: vin=12v vout=1.8v fsw=400khz fig. 7: output voltage regulation vs. current fig. 8: bode plot conditions: vin=12v vout=1.8v iout=15a fsw=400khz phase-margin = 59.3o gain-margin = -18.9db fc = 56.6khz downloaded from: http:///
5 www.irf.com fig. 9: thermograph (with heatsink) c o n d i t i o n s : v i n = 1 2 v v o u t = 1 . 8 v i o u t = 1 5 a fsw = 400khz a m b i e n t t e m p . = 4 5 o c airflow = 300lfm s t a b i l i z i n g t i m e = 1 5 m i n . fig. 10: thermograph (no heatsink) c o n d i t i o n s : v i n = 1 2 v v o u t = 1 . 8 v i o u t = 1 2 a fsw = 400khz a m b i e n t t e m p . = 4 5 o c airflow = 300lfm s t a b i l i z i n g t i m e = 1 5 m i n . 83.8 82.9 ma x 83.2 ma x 83.2 *>89.2c *<24.1c 30.0 40.0 50.0 60.0 70.0 80.0 direction of airflow ma x 92.9 ma x 92.9 74.9 77.9 *>97.4c *<19.8c 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 direction of airflow downloaded from: http:///
www.irf.com 6 fig. 11: power up sequence fig. 12: power down sequence fig. 13: power down C close up conditions: vin=12v vout=1.8v iout=15a fsw=400khz conditions: vin=12v vout=1.8v iout=15a fsw=400khz for close- up, see fig. 13 conditions: vin=12v vout=1.8v iout=15a fsw=400khz downloaded from: http:///
7 www.irf.com fig. 14: output voltage ripple fig. 15: short circuit protection fig. 16: over-voltage protection conditions: vin=12v vout=1.8v iout=15a fsw=400khz ripple = 11.6mvp-p conditions: vin=12v vout=1.8v iout=15a fsw=400khz conditions: vin=12v vout=1.8v fsw=400khz hiccups until short circuit is removed downloaded from: http:///
www.irf.com 8 fig. 17: i out transient step-up 50% - 75% fig. 18: i out transient step-down 75% - 50% fig. 19: i out transient step-up 50% - 100% fig. 20: i out transient step-down 100% - 50% step-up 50% to 75% conditions: vin=12v vout=1.8v fsw=400khz - 42.0mv peak step-down 75% to 50% conditions: vin=12v vout=1.8v fsw=400khz + 41.0mv peak step-up 50% to 100% conditions: vin=12v vout=1.8v fsw=400khz - 85.0mv peak step-down 100% to 50% conditions: vin=12v vout=1.8v fsw=400khz + 81.0mv peak downloaded from: http:///
9 www.irf.com adjusting the over-current limit r9 is the resistor used to adjust the over-current trip point. the trip point corresponds to the peak inductor current indicat ed on the x-axis of fig. 21. (note: fig. 21 is based on ip1203 tblk = 125c. the trip point will be higher than expected if the referenc e board is cool and is being used for short circuit testing.) fig. 21: r ocset vs. over-current trip point 15 20 25 30 35 40 45 50 200 220 240 260 280 300 320 340 360 380 400 switching frequency (khz) ? fig. 22: r10 vs. frequency 5 10 15 20 25 30 35 40 45 50 55 6 8 10 12 14 16 18 20 22 24 over-current trip point (amps) 5 25 45 65 85 105 125 145 165 185 205 vout = 1.5v fsw = 300khz l = 1uh t bl k = 125 0 c vin=12v vin=5.5v downloaded from: http:///
www.irf.com 10 fig. 23: component placement top layer fig. 24: component placement bottom layer fig. 25: top copper layer fig. 26: 1 st mid copper layer downloaded from: http:///
11 www.irf.com fig. 27: 2 nd mid copper layer fig. 28: 3 rd mid copper layer fig. 29: 4 th mid copper layer fig. 30: bottom copper layer downloaded from: http:///
www.irf.com 12 fig. 31: heatsink photo fig. 32: mechanical outline drawing of heatsink tolerances are 0.38 (0.015) downloaded from: http:///
13 www.irf.com fig. 33: reference design schematic ocset 16 v 1 vsw s 19 vsw 18 cc 9 pgnd 5 pgnd 7 v 14 ss 8 pgood 13 sync 15 fb 10 fbs 11 r 12 pgnd 2 pgnd 4 pgnd 3 pgnd 17 pgnd 20 pgnd 21 vcc_bypass 6 vsw 22 v 23 v 24 inin ins ref t u1 ip1203 c7 100pf c5 2.2uf c6 0.1uf c4 10uf c8 33pf c10 8200pf r1 10k r4 10k r5 249 r10 21.0k(400khz) r3 12.1k c3 10uf c1 10uf r2 15k c9 1000pf r9 37.4k vsw l1 1.2uh c13 100uf c14 100uf c15 22uf tp1 vin tp2 pgnd tp3 vout tp4 pgnd r80 c18 0.1uf vins pgnds vouts r6 15k r7 12.1k c16 22uf c2 10uf j1 vin j2 pgnd j3 vout j4 pgnd c17 22uf c12 100uf c11 100pf ss tp5 pgood tp6 sync tp7 vsw downloaded from: http:///
www.irf.com 14 quantity designator type 1 type 2 value 1 value 2 tolerance package manufacturer manu facturer p/n 4 c1, c2, c3, c4 capacitor x7r 10.0uf 16v 10% 1206 tdk c3216x7r1c106kt 1 c10 capacitor x7r 8200pf 50v 10% 0603 koa x7r0603httd822k 2 c11, c7 capacitor npo 100pf 50v 5% 0603 phycomp 0603cg101j9b20 3 c12, c13, c14 capacitor x5r 100uf 6.3v 20% 1210 tdk c3225x5r0j107m 3 c15, c16, c17 capacitor x5r 22.0uf 6.3v 20% 1206 tdk c3216x5r0j226m 2 c18, c6 capacitor x7r 0.100uf 16v 10% 0603 murata grm188r71c104ka01d 1 c5 capacitor x5r 2.20uf 6.3v 10% 0603 murata grm39x5r225k6.3 1 c8 capacitor npo 33.0pf 50v 5% 0603 koa npo0603httd330j 1 c9 capacitor cog 1000pf 100v 5% 0603 tdk c1608cog2a102j 1 h1 hardware heatsink 16 fins 0.400" - 10.6mm x 10.6mm aavid/ thermalloy np974686 rev 1 1 l1 inductor metal composite 1.20uh 22a 20% smt delta electronics mpl104-1r2ir 2 r1, r4 resistor thick film 10.0k 1/10w 1% 0603 koa rk73h1j1002f 1 r10 resistor thick film 21.0k 1/10w 1% 0603 koa rk73h1jltd2102f 2 r2, r6 resistor thick film 15.0k 1/10w 1% 0603 koa rk73h1j1502f 2 r3, r7 resistor thick film 12.1k 1/10w 1% 0603 koa rk73h1jltd1212f 1 r5 resistor thick film 249 1/10w 1% 0603 koa rk73h1jltd2490f 1 r8 resistor carbon film 0 1/16w <50m 0603 rohm mcr03ezhj000 1 r9 resistor thick film 37.4k 1/10w 1% 0603 koa rk73h1j3742f 7 pgnd, pgnd, pgood, sync, vin, vout, vsw hardware test point 90 mils 112 x 150 mils - smt keystone 5016 1 u1 ip1203 lga unit - - - 9mm x 9mm irf - table 1: reference design bill of materials refer to the following application notes for detailed guidelines and suggestions when implementing ipowir technology products: an-1028: recommended design, integration and rework guidelines for international rectifiers ipowir technology bga and lga and packages this paper discusses optimization of the layout design for mounting ipowir bga and lga packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations. topics discussed includes pcb layout placement, and via interconnect suggestions, as well as soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. an-1030: applying ipowir products in your thermal environment this paper explains how to use the power loss and soa curves in the data sheet to validate if the operating conditions and thermal environment are within the safe operating area of the ipowir product. an-1047: graphical solution for two branch heatsinking safe operating area detailed explanation of the dual axis soa graph and how it is derived. use of this design for any application should be fully verified by the customer. international rectifier cannot guarantee suitability for your applications, and is not liable for any result of usage for such applications including, without limitation, personal or property damage or violation of third party intellectual property rights. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 downloaded from: http:///

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